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ISL97632
Data Sheet April 10, 2007 FN9239.2
White LED Driver with Digital Dimming
The ISL97632 represents an efficient and highly integrated PWM boost LED driver that is suitable for 1.8" to 3.5" LCDs that employ 2 to 6 white LEDs for backlighting. With integrated Schottky diode, OVP, and dynamic digital dimming capability, the ISL97632 provides a simple, reliable, and flexible solution to the backlight designers. The ISL97632 features a simple single-wire digital interface that provides a 5-bit dimming control. The dimming signal adjusts the FB voltage and therefore the LED brightness in a DC manner in 32 linear steps. An EN pin can be used to provide a zero brightness setting or shutdown power saving function. The ISL97632 is available in the 8 Ld DFN (2mmx3mm) package. There are 14V, 18V, and 26V OVP options that are suitable for 3, 4, and 6 LEDs backlight applications respectively. The ISL97632 is specified for operation over the -40C to +85C ambient temperature at input voltage from 2.4V to 5.5V.
Features
* 5-Bit Digital Dimming Control * Drives up to 6 LEDs in Series * OVP (14V, 18V and 26V for 3, 4, and 6 LEDs applications) * Integrated Schottky Diode * 2.4V to 5.5V input * 86% Efficiency * 1.4MHz Switching Frequency Allows Small LC * Enable for Shutdown Function or Zero Brightness Setting * 1A Shutdown Current * Internally Compensated * 8 Ld DFN (2mmx3mm) * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* LED backlighting for - Cell phones - Smartphones - MP3 - PMP - Automotive Navigation Panel - Portable GPS
Pinout
ISL97632 (8 LD 2x3 TDFN) TOP VIEW
GND VIN EN SDIN
1 2 3 4
8 7 6 5
LX VOUT FBSW FB
Ordering Information
PART NUMBER (Note) PART MARKING ELB TAPE & REEL (QTY) PACKAGE (Pb-Free) PKG. DWG.#
Typical Application Circuit
10H or 22H VIN
ISL97632IRT14Z-T
13" 8 Ld 2x3 TDFN L8.2x3A (6k pcs.) 13" 8 Ld 2x3 TDFN L8.2x3A (1k pcs.) 13" 8 Ld 2x3 TDFN L8.2x3A (6k pcs.) 13" 8 Ld 2x3 TDFN L8.2x3A (1k pcs.) 13" 8 Ld 2x3 TDFN L8.2x3A (6k pcs.) 13" 8 Ld 2x3 TDFN L8.2x3A (1k pcs.)
ISL97632IRT14Z-TK ELB
VIN EN SDIN FBSW FB LX VOUT
ISL97632IRT18Z-T
ELC
ISL97632IRT18Z-TK ELC ISL97632IRT26Z-T ELD
ISL97632IRT26Z-TK ELD
GND
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL97632
Absolute Maximum Ratings (TA = +25C)
Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V LX Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V FBSW Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) JC (C/W) TDFN Package (Notes 1, 2). . . . . . . . . 70 10.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed over temperature of -40C to +85C unless otherwise stated. Typical values are for information purposes only at TJ = TC = TA = +25C.
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER VIN IIN Supply Voltage Supply Current
VIN = VEN = 3V CONDITION MIN 2.4 EN = 3V, enabled, not switching EN = 0V, disabled 0.8 TYP MAX 5.5 1.5 1 1,300 90 400 ILX = 100mA VLX = 28V Serial interface setting = 15 (center) Serial interface setting = S (S = 0,1..31) Serial interface setting = 0 90 95 9.8 + 5.68 x S 9.8 1 10 IDIODE = 100mA, TA = +25C ISL97632IRT14Z ISL97632IRT18Z ISL97632IRT26Z 600 14 18 26 28 0.6 1.5 SDIN = low SDIN = low SDIN = low SDIN = high 15 90 215 3 45 120 850 1,450 95 470 900 1 100 1,600 UNIT V mA A kHz % mA m A mV mV mV A mV V V V V V s s s s
DESCRIPTION
Fsw DMAX ILIM RSW(LX) ILEAK VFB
Switching Frequency Maximum Duty Cycle LX Current LX Switch ON-Resistance LX Switch Leakage Current Feedback Voltage
IFB RSW(FBSW) VDIODE OVP
FB Pin Bias Current FBSW Switch ON-Resistance Schottky Diode Forward Voltage Overvoltage Protection
VFB = 95mV
VIL VIH tLOGIC1 tLOGIC0 tLOGIC-LOAD tLOGIC-HIGH
Logic Low Voltage Logic High Voltage Timing Range for Logic 1 Timing Range for Logic 0 Timing Range for Load Minimum Valid SDIN High Time
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ISL97632 Block Diagram
VIN (2.4V to 5.5V) CIN VIN EN L
LX
1.4MHZ OSCILLATOR AND RAMP GENERATOR
ISL97632
VOUT COUT
PWM COMPARATOR
PWM LOGIC CONTROLLER
FET DRIVER
2 to 6 LEDs
CURRENT SENSE GND FBSW EN
GM AMP COMPENSATION SDIN
GM AMPLIFIER
FB 10 - 186mV BANDGAP REFERENCE GENERATOR RSET
SERIAL INTERFACE
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME GND VIN EN SDIN FB FBSW VOUT LX Ground Pin. Connect to local ground. Input Supply Pin. Connect to the input supply voltage, the inductor and the input supply decoupling capacitor. Enable Pin. Connect to enable signal to turn-on or off the device. Active High. Single-Wire XSD Digital Interface. Feedback Pin. Connect to the cathode of bottom LED and the sense resistor. Optional FB Disconnect Switch. Output Pin. Connect to the anode of the top LED and the output filter capacitor. Switching Pin. Connect to inductor. DESCRIPTION
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ISL97632 Single-Wire Serial Interface
30s 100s 220s
'1'
'0'
'1'
'0'
'0'
'LOAD'
0
200
400
600
800
1000
1200
s
FIGURE 1. SINGLE-WIRE XSD INTERFACE
The ISL97632 uses a simple single-wire serial interface for programming the output brightness of the LEDs. A 5-bit interface is used to give a total of 32 levels of output brightness. The interface uses a normally high connection for use with open-drain driving schemes and Intersil's proprietary XSD bus. When held low for between 15s and 45s, the interface registers a logic 1. When held low for between 90s and 120s the interface registers a logic 0. When held low for greater that 215s, the interface loads the last 5 bits into the brightness control register and updates the brightness level. The required minimum high time is 3s. This simple single-wire programming is summarized as follow: * Logic 0 = Negative pulse >90s and <120s * Logic 1 = Negative pulse >15s and <45s * Load = Negative pulse >215s Figure 1 shows an example of programming a binary code of 10100 and load it in to the device serial register. The serial interface is automatically reset to 0 when the device is disabled, or enters UVLO. Therefore, when the part is enabled, the output brightness is automatically set to the minimum level.
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ISL97632 Typical Performace Curves
90 4.2V IN 4 LEDs OUT (15H) 85 80 EFFICIENCY (%) 75 70 65 60 55 50 0 5 10 15 20 25 30 35 40 45 IOUT (mA) 3.6V IN 4 LEDs OUT (22H) 0 - 0.2 0 1 2 VIN (V) 3 4 5 3.6V IN 4 LEDs OUT (10H) 3.6V IN 4 LEDs OUT (15H) 4.2V IN 4 LEDs OUT (10H) 4.2V IN 4 LEDs OUT (22H) Iq (mA) IO (mA) 5 10 15 VOUT (V) 20 25 30 0.6 0.4 0.2 0.8 1
FIGURE 2. EFFICIENCY vs LED CURRENT
FIGURE 3. QUIESCENT CURRENT vs VIN (ENAB = HI)
20.08
19.76 19.74
20.04 19.72 IO (mA) 20.00 19.70 19.68 19.66 19.64 19.92 0 19.62 2.5
19.96
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
FIGURE 4. LOAD REGULATION (VIN = 4V)
FIGURE 5. LINE REGULATION
40 35 30 IO (mA) 25 20 15 10 5 0 0 5 10 15 20 25 30 35 CODE = DECIMAL RSET = 4.7
FIGURE 6. ILED vs PROGRAMMING CODES
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FN9239.2 April 10, 2007
ISL97632 Detailed Description
The ISL97632 uses a constant frequency, current mode control scheme to provide excellent line and load regulation. There are three OVP models for driving 3, 4, and 6 LEDs and their OVP thresholds are set at 14V, 18V, and 26V respectively. The ISL97632 operates from an input voltage of 2.4V to 5.5V and ambient temperature from -40C to +85C. The switching frequency is around 1.45MHz and allows the driver circuit to employ small LC components. The forward current of the LED is set using the RSET resistor. In the steady state mode, the LED current is given by Equation 1:
V FB ( S ) 9.8mV + 5.68mV x S I LED ( S ) = ------------------- = ------------------------------------------------------R SET R SET (EQ. 1)
resume previous setting, the device needs to be reprogrammed.
Output Disconnect
The ISL97632 features a FBSW feedback disconnect switch that can be used in between the LED and Rset for an optional short-circuit protection. For example, the user may build an external short circuit detection to monitor the VOUT. If the VOUT goes low due to one or more LEDs which are shorted, the circuit can release the EN and FBSW switch to disconnect the LEDs.
Components Selection
The input capacitance is typically 0.22F to 4.7F. The output capacitor should be in the range of 0.22F to 1F. X5R or X7R type of ceramic capacitors of the appropriate voltage rating are recommended. When choosing an inductor, make sure the average and peak current ratings are adequate by using the following equations (80% efficiency assumed):
I LED V OUT I LAVG = -------------------------------0.8 V IN 1 I LPK = I LAVG + -- I L 2 V IN ( V OUT - V IN ) I L = -------------------------------------------------L V OUT f OSC (EQ. 2)
where S is the 5-bit Serial Interface Setting or Digital code from 0 to 31 programmed in the XSD single-wire interface. The default setting is 0 and the VFB is at minimum.
Dimming Control
The ISL97632 powers up to provide minimium current. By programming the digital code with the Intersil's XSD singlewire interface as shown in Figure 1, the current can be changed linearly with the digital code from 0 to 31. Figure 6 shows LED current versus the programming codes.
(EQ. 3)
Overvoltage Protection
The ISL97632 comes with overvoltage protection. The OVP trip points are at 14V, 18V, and 26V for ISL97632IRT14Z, ISL97632IRT18Z, and ISL97632IRT26Z respectively. The maximum numbers of LEDs and OVP threshold are shown in Table 1. When the device reaches the OVP, the LX stops switching, disabling the boost circuit until VOUT falls about 7% below the OVP threshold. At this point, LX will be allowed to switch again. The OVP event will not cause the device to shutdown
TABLE 1. PART NO. ISL97632IRT14Z ISL97632IRT18Z ISL97632IRT26Z OVP 14V 18V 26V MAX NO. OF LEDS 3 4 6 MAX ILED 70mA 50mA 30mA
(EQ. 4)
Where: * IL is the peak-to-peak inductor current ripple in Amps * L is the inductance in H. * fOSC is the switching frequency, typically 1.45MHz The ISL97632 supports a wide range of inductance values (10H~82H). For lower inductor values or lighter loads, the boost inductor current may become discontinuous. For high boost inductor values, the boost inductor current will be in continuous mode. In addition to the inductor value and switching frequency, the input voltage, the number of LEDs and the LED current also affect whether the converter operates in continuous conduction or discontinuous conduction mode. Both operating modes are allowed and normal. The discontinuos conduction mode yields lower efficiency due to higher peak current.
There are three OVP options so that the 3 LEDs application should use the 14V OVP device and the 6 LEDs application should use the 26V OVP device. An output capacitor that is only rated for the required voltage range can therefore be used which will optimize the component costs in some cases.
Compensation
The product of the output capacitor and the load create a pole while the inductor creates a right half plane zero. Both attributes degrade the phase margin but the ISL97632 has an internal compensation network that ensures the device operates reliabily under the specified conditions. The internal compensation and the highly integrated functions of the ISL97632 make it a design friendly device to be used in high volume high reliability applications.
Shut-Down
An active high EN pin is normally on but this pin can be used as a shutdown power saving function or zero brightness setting. When taken low the EN pin places the ISL97632 into power down mode down where the supply current is reduced to less than 1A. The EN pin cannot be used as PWM input as the part resets to 0 whenever EN is low. To 6
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ISL97632 Applications
Efficiency Improvement
Figure 2 shows the efficiency measurements. The choice of the inductor has a significant impact on the power efficiency. As shown in Equation 4, the higher the inductance, the lower the peak current therefore the lower the conduction and switching losses. On the other hand, it has also a higher series resistance. Nevertheless, the efficiency improvement from lowering the peak current is greater than the impact of the resistance increase with larger value of inductor. Efficiency can also be improved for systems that have high supply voltages. Since the ISL97632 can only supply from 2.4V to 5.5V, VIN must be seperated from the high supply voltage for the boost circuit as shown in Figure 7 and the efficiency improvement is shown in Figure 8.
C3 0.22 D1 D2 D3 D4 25mA VIN LX D5 D6 VOUT ISL97632 FBSW EN FB SDIN GND R1 4
Vs = 12V C1 1
L1 1 22 2
VIN = 2.7V TO 5.5V C2 0.1
FIGURE 7. SEPERATE HIGH INPUT VOLTAGE FOR HIGHER EFFICIENCY OPERATION
MOSFET connected in cascode fashion to achieve higher output voltage. A conceptual 8 LEDs driver circuit is shown in Figure 9. A 60V logic level N-Channel MOSFET is configured such that its drain ties between the inductor and the anode of schottky diode, its gate ties to the input, and its source ties to the ISL97632 LX node connecting to the drain of the internal switch. When the internal switch turns on, it pulls the source of M1 down to ground, and LX conducts as normal. When the internal switch turns off, the source of M1 will be pulled up by the follower action of M1, limiting the maximum voltage on the ISL97632 LX pin to below Vin, but allowing the output voltage to go much higher than the breakdown limit on the LX pin. The switch current limit and maximum duty cycle will not be changed by this setup, so input voltage will need to be carefully considered to make sure that the required output voltage and current levels are achievable. Because the source of M1 is effectively floating when the internal LX switch is off, the drain-to-source capacitance of M1 may be sufficient to capacitively pull the node high enough to breaks down the gate oxide of M1. To prevent this, VOUT should be connected to VIN, allowing the internal schottky to limit the peak voltage. This will also hold the VOUT pin at a known low voltage, preventing the built in OVP function from causing problems. This OVP function is effectively useless in this mode as the real output voltage is outside its intended range. If the user wants to implement their own OVP protection (to prevent damage to the output capacitor, they should insert a zener from vout to the FB pin. In this setup, it would be wise not to use the FBSW to FB switch as otherwise the zener will have to be a high power one capable of dissipating the entire LED load power. Then the LED stack can then be connected directly to the sense resistor and via a 10k resistor to FB. A zener can be placed from Vout to the FB pin allowing an over voltage event to pull up on FB with a low breakdown current (and thus low power zener) as a result of the 10k resistor.
VIN = 2.7V TO 5.5V C1 1 1 L1 2.2 M1 VOUT LX ISL97632 FBSW EN FB SDIN GND VIN C2 0.1 2 D0 10BQ100 C3 4.7 D1 D2 D3 D4 D5 R1 6.3 D6
90
VS = 12V VS = 9V
85 EFFICIENCY (%)
80
FQT13N06L SK011C226KAR
75
VIN = 4V 6 LEDs L1 = 22H R1 = 4 0 5 10 15 20 ILED (mA) 25 30
70
D7 D8
FIGURE 8. EFFICIENCY IMPROVEMENT WITH 9V AND 12V INPUTS
8 LEDs Operation
For medium size LCDs that need more than 6 low power LEDs for backlighting, such as a Portable Media Player or Automotive Navigation Panel displays, the voltage range of the ISL97632 is not sufficient. However, the ISL97632 can be used as an LED controller with an external protection 7
FIGURE 9. CONCEPTUAL 8 LEDS HIGH VOLTAGE DRIVER
SEPIC Operation
For applications where the output voltage is not always above the input voltage, a buck or boost regulation is needed. A SEPIC (Single Ended Primary Inductance
FN9239.2 April 10, 2007
ISL97632
Converter) topology, (shown in Figure ), can be considered for such an application. A single cell Li-Ion battery operating a cellphone backlight or flashlight is one example. The battery voltage is between 2.5V and 4.2V depending on the state of charge. On the other hand, the output may require only one 3V to 4V medium power LED for illumination because the light guard of the backlight assembly is optimized or it is a cost efficiency trade off reason. In fact, a SEPIC configured LED driver is flexible enough to allow the output to be well above or below the input voltage, unlike the previous example. Another example is when the number of LEDs and input requirements are different from platform to platform, a common circuit and PCB that fit all the platforms, in some cases, may be beneficial enough that it outweights the disadvantage of adding additional component cost. L1 and L2 can be a coupled inductor in one package.
VIN = 2.7V to 5.5V 1 L1 2 22 C1 1 VIN C2 0.1 EN SDIN LX VOUT FBSW FB EFFICIENCY (%) GND R1 1 72 VA C3 1 VB L2 C4 22 0.22 D1
boost regulator operation, except the lowest reference point is at -VIN. The output is approximated as:
D V OUT = V IN ----------------(1 - D) (EQ. 5)
where D is the on-time of the PWM duty cycle. The convenience of SEPIC comes with some trade off in addition to the additional L and C costs. The efficiency is usually lowered because of the relatively large efficiency loss through the Schottky diode if the output voltage is low. The L2 series resistance also contributes additional loss. Figure 11 shows the efficiency measurement of a single LED application as the input varies between 2.7V and 4.2V. Note, VB is considered the level-shifted LX node of a standard boost regulator. The higher the input voltage, the lower the VB voltage will be during PWM on period. The result is that the efficiency will be lower at higher input voltages because the SEPIC has to work harder to boost up to the required level. This behavior is the opposite to the standard boost regulator's and the comparison is shown in Figure 11.
76 VIN = 2.7V
FIGURE 10. SEPIC LED DRIVER
68
VIN = 4.2V 1 LED L1 = L2 = 22H C3 = 1F R1 = 4.7
The simplest way to understand SEPIC topology is to think about it as a boost regulator in which the input voltge is level shifted downward at the same magnitude and the lowest reference level starts at -VIN rather than 0V. The SEPIC works as follows; assume the circuit in Figure 10 operates normally when the ISL97632 internal switch opens and it is in the PWM off state after a short duration where few LC time constants elapsed, the circuit is considered in the steady-state within the PWM off period that L1 and L2 are shorted. VB is therefore shorted to the ground and C3 is charged to VIN with VA = VIN. When the ISL97632 internal switch closes and the circuit is in the PWM on state, VA is now pulled to ground. Since the voltage in C3 cannot be changed instantenously, VB is shifted downward and becomes -VIN. The next cycle when the ISL97632 switch opens, VB boosts up to the targetted output like the standard
64
60 0 5 10 ILED (mA) 15 20
FIGURE 11. EFFICIENCY MEASUREMENT OF A SINGLE LED SEPIC DRIVER
PCB Layout Considerations
The layout is very important for the converter to function properly. RSET must be located as close as possible to the FB and GND pins. Longer traces to the LEDs are acceptable. Similarly, the supply decoupling cap and the output filter cap should be as close as possible to the VIN and VOUT pins. The heat of the IC is mainly dissipated through the thermal pad of the package. Maximize the copper area connected to this pad if possible. In addition, a solid ground plane is always helpful for the EMI performance.
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FN9239.2 April 10, 2007
ISL97632 Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.15 C A A D 2X 0.15 C B
L8.2x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A
E
MIN 0.70 -
NOMINAL 0.75 0.20 REF
MAX 0.80 0.05
NOTES -
A1 A3 b D
6 INDEX AREA B
0.20
0.25 2.00 BSC
0.32
5,8 -
TOP VIEW
D2 E
// 0.10 C
1.50
1.65 3.00 BSC
1.75
7,8 -
E2
A 0.08 C
1.65
1.80 0.50 BSC
1.90
7,8 -
e k L N 0.20 0.30
C SEATING PLANE
SIDE VIEW
A3
0.40 8 4
0.50
8 2 3 Rev. 0 6/04
D2 (DATUM B) 1 2 D2/2
7
8
Nd NOTES:
6 INDEX AREA (DATUM A)
NX k
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D.
E2 E2/2
4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N N-1 NX b 8 e (Nd-1)Xe REF. BOTTOM VIEW (A1) NX (b) 5 SECTION "C-C" CC e FOR EVEN TERMINAL/SIDE TERMINAL TIP L C L 5 0.10 M C AB
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN9239.2 April 10, 2007

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